1. Field of the Invention
The present invention generally relates to semiconductor packages and manufacturing methods of the semiconductor packages. More specifically, the present invention relates to a semiconductor package including a semiconductor chip, a resin part configured to cover a part of the semiconductor chip, and a wiring structure configured to electrically connect to the semiconductor chip; and a manufacturing method of the semiconductor package.
2. Description of the Related Art
Conventionally, a semiconductor package including a semiconductor chip, a resin part configured to cover a part of the semiconductor chip, and a wiring structure configured to be electrically connected to a semiconductor chip has been known. An example of such a semiconductor package is discussed below.
FIG. 1 is a cross-sectional view showing a related art semiconductor package. As shown in FIG. 1, a semiconductor package 100 includes a semiconductor chip 200, a resin part 300, and a wiring structure 400.
The semiconductor chip 200 includes a chip main body 210 and electrode pads 220. The chip main body 210 has a structure where a semiconductor integrated circuit (not shown in FIG. 1) and others are formed on a thin plate semiconductor substrate (not shown in FIG. 1) made of silicon. The electrode pads 220 are formed on the chip main body 210. Surfaces 220a of the electrode pads 220 are exposed from a surface of the chip main body 210. The electrode pads 220 are electrically connected to the semiconductor integrated circuit (not shown in FIG. 1) of the chip main body 210. A surface 200a of the semiconductor chip 200, which is a surface of the chip main body 210 where the electrode pads 220 are formed, is flat. In other words, the surfaces 220a of the electrode pads 220 are substantially flush with the surface of the chip main body 210.
The resin part 300 is provided so as to cover a surface 200b which is a side surface of the semiconductor chip 200. The resin part 300 is not provided on the surface 200a of the semiconductor chip 200 and a surface 200c which is an opposite surface of the surface 200a. The surfaces 200a and 200c of the semiconductor chip 200 are completely exposed from (not covered by) the resin part 300. In other words, the resin part 300 comes in contact with only the surface 200b of the semiconductor chip 200 and does not come in contact with the surfaces 200a and 200c of the semiconductor chip 200. A surface 300a of the resin part 300 is substantially flush with the surface 200a of the semiconductor chip 200 (the surfaces 220a of the electrode pads 220 and the surface of the chip main body 210). In addition, a surface 300b of the resin part 300 is substantially flush with the surface 200c of the semiconductor chip 200. In the semiconductor chip 200, the surface 200a may be called a circuit forming surface; the surface 200b may be called a side surface; and the surface 200c may be called a rear surface.
The wiring structure 400 includes a first wiring layer 410, a second wiring layer 420, a third wiring layer 430, a first insulation layer 440, a second insulation layer 450, a third insulation layer 460, and a solder resist layer 470.
The first insulation layer 440 is formed on the surface 200a of the semiconductor chip 200 and the surface 300a of the resin part 300. The first wiring layer 410 is formed on the first insulation layer 440. The first wiring layer 410 is electrically connected to the electrode pads 220 of the semiconductor chip 200 via first via-holes 440x piercing the first insulation layer 440. The second insulation layer 450 is formed on the first insulation layer 440 so as to cover the first wiring layer 410.
The second wiring layer 420 is formed on the second insulation layer 450. The second wiring layer 420 is electrically connected to the first wiring layer 410 via second via holes 450x piercing the second insulation layer 450. The third insulation layer 460 is formed on the second insulation layer 450 so as to cover the second wiring layer 420. The third wiring layer 430 is formed on the third insulation layer 460. The third wiring layer 430 is electrically connected to the second wiring layer 420 via third via holes 460x piercing the third insulation layer 460.
The solder resist layer 470 is formed on the third insulation layer 460 so as to cover the third wiring layer 430. The solder resist layer 470 has opening parts 470x in which parts of the third wiring layer 430 are exposed. The third wiring layer 430 exposed in the opening parts 470x of the solder resist layer 470 functions as electrode pads connected to a motherboard and others.
FIG. 2 through FIG. 6 are views showing a manufacturing process of the related art semiconductor package. In FIG. 2 through FIG. 6, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and explanation thereof may be omitted. In each of FIG. 2 through FIG. 5, (a) is a plan view and (b) is a cross-sectional view taken along a line A-A. The manufacturing process of the related art semiconductor package is discussed with reference to FIG. 2 through FIG. 6. In FIG. 2 through FIG. 5, illustration of the electrode pads 220 is omitted.
First, in a step shown in FIG. 2, a semiconductor wafer is cut into pieces so that plural semiconductor chips 200 are manufactured. Then, the plural semiconductor chips 200 are provided on a surface 500a of a supporting body 500 so that the surfaces (circuit forming surface) 200a face a surface 500a of the supporting body 500. Plural semiconductor chips 200 can be fixed to the surface 500a of the supporting body 500 by, for example, an adhesive material (not shown in FIG. 2).
Next, in a step shown in FIG. 3, the resin part 300 is formed on the surface 500a of the supporting body 500 by press molding or the like. The resin part 300 is configured to seal plural semiconductor chips 200. More specifically, epoxy resin or the like which is a material of the resin part 300 is applied on the surface 500a of the supporting body 500 so that plural semiconductor chips 200 are sealed. In addition, by heating and pressing the epoxy resin or the like, the epoxy resin is cured so that the resin part 300 is formed.
Next, in a step shown in FIG. 4, the supporting body 500 is removed. The supporting body 500 can be removed by using, for example, an etching technique. Furthermore, in a case where the supporting body is fixed to the semiconductor chip 200 and the resin part 300 by a heat peeling tape, the supporting body 500 can be removed by applying designated heat. As a result of this, the surfaces 200a of the semiconductor chips 200 are exposed from the surface 300a of the resin part 300.
Next, in a step shown in FIG. 5, a part of the resin part 300 covering the surfaces 200c of the semiconductor chips 200 is removed so that the surfaces 200c of the semiconductor chips 200 are exposed from the surface 300b of the resin part 300. As a result of this, the resin part 300 comes in contact with only the surface (side surface) 200b of the semiconductor chip 200 and therefore the surfaces 200a and 200c are exposed from the resin part 300. The reason why a part of the resin part 300 covering the surface 200c of the semiconductor chip 200 is removed is to transfer the heat generated by the semiconductor chip 200. If a part of the resin part 300 covering the surface 200c of the semiconductor chip 200 is not removed, the temperature of the semiconductor chip 200 is increased so that operation of the semiconductor chip 200 may be obstructed.
Next, in a step shown in FIG. 6, by a known method, the first insulation layer 440, the first wiring layer 410, the second insulation layer 450, the second wiring layer 420, the third insulation layer 460, the third wiring layer 430, and the solder resist layer 470 having the opening parts 470x are formed, in this order, on the surface 200a of the semiconductor chip 200 and the surface 300a of the resin part 300. After the step shown in FIG. 6, by cutting the structural body shown in FIG. 6 in cutting positions C, the semiconductor package 100 shown in FIG. 1 is completed. See International Publication Official Gazette No. 02/33751 and International Publication Official Gazette No. 02/15266.
However, in the manufacturing method of the related art semiconductor package, as shown in FIG. 5, in order to transfer heat generated by the semiconductor chip 200, the surface (rear surface) 200c of the semiconductor chip 200 is exposed from the resin part 300. As a result of this, the semiconductor chip 200 is fixed to the resin part 300 by only the surface (side surface) 200b. Therefore, it is not possible to secure a sufficient area of the contact part between the semiconductor chip 200 and the resin part 300. As a result of this, the semiconductor chip 200 may fall down (separate) from the resin part 300 and the strength of the semiconductor package 100 may not be sufficient.